Selected Publications:
2022
1. The Larger The Fairer? Small Neural Networks Can Achieve Fairness for Edge Devices [arXiv]
Yi Sheng, Junhuan Yang, Yawen Wu, Kevin Mao, Yiyu Shi, Jingtong Hu, Weiwen Jiang and Lei Yang
In Proc. of Design Automation Conference (DAC), 2022.
2. RT-DNAS: Real-time Constrained Differentiable Neural Architecture Search for 3D Cardiac Cine MRI Segmentation [arXiv]
Qing Lu, Xiaowei Xu, Shunjie Dong, Callie Hao, Lei Yang, Cheng Zhuo, and Yiyu Shi
In Proc. of Medical Image Computing and Computer Assisted Interventions (MICCAI), 2022.
3. Automated Architecture Search for Brain-inspired Hyperdimensional Computing [arXiv]
Junhuan Yang, Yi Sheng, Sizhe Zhang, Ruixuan Wang, Kenneth Foreman, Mikell Paige, Xun Jiao, Weiwen Jiang, and Lei Yang
In Proc. of AutoML Conference Work-in-Progress (AutoML), 2022.
2021
4. FL-DISCO : Federated Generative Adversarial Network for Graph-based Molecule Drug Discovery
D. Manu, Y. Sheng, J. Yang, J. Deng, T. Geng, A. Li, C. Ding, W. Jiang, L. Yang
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD 2021), Virtaul Conference, Nov. 2021.
5. Federated Contrastive Learning for Dermatological Disease Diagnosis via On-device Learning
Y. Wu, D. Zeng, Z. Wang, Y. Sheng, L. Yang, A. James, Y. Shi, J. Hu
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD 2021), Virtaul Conference, Nov. 2021.
6. Can Noise on Qubits Be Learned in Quantum Neural Network? A Case Study on QuantumFlow
Z. Liang, Z. Wang, J. Yang, L. Yang, J. Xiong, Y. Shi, W. Jiang
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD 2021), Virtaul Conference, Nov. 2021.
7. Co-Exploration of Graph Neural Network and Network-on-Chip Design Using AutoML
D. Manu, S. Huang, C. Ding, L. Yang
ACM 2021 on Great Lakes Symposium on VLSI (GLVLSI 2021), Virtaul Conference, June. 2021.
8. HMC-TRAN : A Tensor-core Inspired Hierarchical Model Compression for Transformer-based DNNs on GPU
S.i Huang, S. Chen, H. Peng, D. Manu, Z. Kong, G. Yuan, L. Yang, S. Wang, H. Liu, C. Ding
ACM 2021 on Great Lakes Symposium on VLSI (GLVLSI 2021), Virtaul Conference, June. 2021.
2020
9. Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip
P. Chen, W. Liu, H. Chen, S. Li, M. Li, L. Yang, N. Guan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Aug, 2020.
10. Standing on the Shoulders of Giants: Hardware and Neural Architecture Co-Search with Hot Start [arXiv]
W. Jiang, L. Yang, S. Dasgupta, J. Hu and Y. Shi
International Conference on Hardware/Software Co-design and System Synthesis CODE+ISSS) in ESWEEK'20
(acceptance rate 94/375=25.1%)
also appears at IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Virtaul Conference, Oct. 2020.
11. Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators [arXiv]
W. Jiang, Q. Lou, Z. Yan, L. Yang, J. Hu, X. S. Hu and Y. Shi
IEEE Transactions on Computers (TC), Accepted, 2020.
12. Hardware/Software Co-Exploration of Neural Architectures [arXiv]
W. Jiang, L. Yang, E. H.-M. Sha, Q. Zhuge, S. Gu, S. Dasgupta, Y. Shi and J. Hu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Accepted, 2020.
13. Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks [arXiv]
L. Yang, Z. Yan, M. Li, H. Kwon, L. Lai, T. Krishana, V. Chandra, W. Jiang, and Y. Shi
Design Automation Conference (DAC), 2020.
(acceptance rate 228/992=23.0%)
14. Co-Exploring Neural Architecture and Network-on-Chip Design for Real-Time Artificial Intelligence (BEST PAPER NOMINATION)
L. Yang*, W. Jiang*, W. Liu, E. H.-M. Sha, Y. Shi and J. Hu
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), Beijing, Jan. 2020.
(acceptance rate 86/263=32.6%; * equal contribution)
2019
15. Achieving Super-Linear Speedup across Multi-FPGA for Real-Time DNN Inference [arXiv] (BEST PAPER NOMINATION)
W. Jiang, E. H.-M. Sha, X. Zhang, L. Yang, Q. Zhuge, Y. Shi and J. Hu
International Conference on Hardware/Software Co-design and System Synthesis CODE+ISSS) in ESWEEK'19
(acceptance rate 66/243=27.2%)
also appears at ACM Transactions on Embedded Computing Systems (TECS), NYC, New York, USA, Oct. 2019.
16. Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search [arXiv]
      (BEST PAPER NOMINATION)
W. Jiang, X. Zhang, E. H.-M. Sha, L. Yang, Q. Zhuge, Y. Shi, and J. Hu
Design Automation Conference (DAC), 2019.
(acceptance rate 204/815=25%)
2018
17. Heterogeneous FPGA-based Cost-Optimal Design for Timing-Constrained CNNs
W. Jiang, E. H.-M. Sha, Q. Zhuge, L. Yang, X. Chen, and J. Hu
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) in ESWEEK'18
(acceptance rate 67/270=24.8%)
also appear at IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Torino, Italy, Oct. 2018.
18. On the Design of Time-Constrained and Buffer-Optimal Self-Timed Pipelines
W. Jiang, E. H.-M. Sha, Q. Zhuge, L. Yang, X. Chen, and J. Hu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Accepted, 2018.
19. Thermal-aware Task Mapping on Dynamically Reconfigurable Network-on-Chip based Multiprocessor System-on-Chip
W. Liu, L. Yang, W. Jiang, L. Feng, N. Guan, W. Zhang, and N. Dutt
IEEE Transactions on Computers (TC), Accepted, 2018.
20. On the Design of Minimal-Cost Pipeline Systems Satisfying Hard/Soft Real-Time Constraints (BEST PAPER AWARD)
W. Jiang, E. H.-M. Sha, Q. Zhuge, L. Yang, H. Dong and X. Chen
IEEE International Conference on Computer Design (ICCD2017@BOSTON)
(acceptance rate 75/258=29.1%)
also appear at IEEE Transactions on Emerging Topics in Computing (TETC), Jan. 2018.
2017
21. Work In Progress: Communication Optimization for Thermal Reliable Many-core Systems
W. Liu, L. Yang, W. Jiang and N. Guan
Proc. International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS), Seoul, South Korea, Oct. 2017.
22. Optimal Functional-Unit Assignment for Heterogeneous Systems under Timing Constraint
W. Jiang, E. H.-M. Sha, X. Chen, L. Yang, L. Zhou and Q. Zhuge
IEEE Transactions on Parallel and Distributed Systems (TPDS), 28(9), 2567-2580, 2017.
23. FoToNoC: A Folded Torus-Like Network-on-Chip based Many-Core Systems-on-Chip in the Dark Silicon Era
L. Yang, W. Liu, W. Jiang, M. Li, P. Chen and E. H.-M. Sha
IEEE Transactions on Parallel and Distributed Systems (TPDS), 28(7), 1905-1918, 2017.
2016
24. Application Mapping and Scheduling for Network-on-Chip-Based MPSoC With Fine-Grain Communication Optimization
L. Yang, W. Liu, W. Jiang, M. Li, J. Yi and E. H. M. Sha
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 24(10), 3027-3040, Oct. 2016.
25. Properties of Self-Timed Ring Architectures for Deadlock-Free and Consistent Configuration Reaching Maximum Throughput
W. Jiang, Q. Zhuge, X. Chen, L. , J. Yi and E. H.-M. Sha
Journal of Signal Processing Systems (JSPS), 84(1), 123-137, Jul. 2016.
26. FoToNoC: A hierarchical management strategy based on folded lorus-like Network-on-Chip for dark silicon many-core systems
      (BEST PAPER NOMINATION)
L. Yang, W. Liu, W. Jiang, M. Li, J. Yi and E. H.-M. Sha
Proc. 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, Jan. 2016.
2015
27. Prevent Deadlock and Remove Blocking for Self-Timed Systems
E. H.-M. Sha, W. Jiang, Q. Zhuge, X. Chen and L. Yang
Proc. International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), Zhangjiajie, China, Nov. 2015.
28. On the Design of High-Performance and Energy-Efficient Probabilistic Self-Timed Systems
E. H.-M. Sha, W. Jiang, Q. Zhuge, L. Yang and X. Chen
Proc. High Performance Computing and Communications (HPCC), NewYork, NY, USA, Aug. 2015.
2014
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